IBM, C-DAC ink MoU to boost India's HPC processor capabilities

IT company IBM and the state-owned Centre for Development of Advanced Computing (C-DAC) have signed a Memorandum of Understanding (MoU) to enhance India's processor design and manufacturing capabilities for High Performance Computing (HPC). 

The collaboration involves the formation of a joint working group to accelerate HPC in India, focusing on processor design, system design, firmware, and application development. This effort also includes contributions to open-source initiatives. 

Through this partnership, IBM and C-DAC will promote IBM’s Power processor for HPC applications across various sectors in India, including startups, MSMEs, research organisations, and academic institutions. The collaboration aims to enhance skills, competencies, and ecosystem development in HPC design research. 

The collaboration also seeks to guide and enable startups and companies in developing reliable HPC systems, support co-development and innovation in various areas, and conduct capacity-building workshops and design reviews for implementation partners, the company said. 

Sandip Patel, Managing Director, IBM India & South Asia said, “As we accelerate the adoption of technologies like AI, the demand for HPC will grow significantly as most HPC systems are created with these workloads in mind. This presents a great opportunity for our country to be among the leaders in this space – provided there are sufficient resources and skills available to scale the industry. This collaboration aims to create such a conducive environment.” 

Under the HPC working group, IBM will collaborate with C-DAC and identified partners to design and build competitive indigenous processors based on the IBM Power architecture. This architecture is specifically tailored for data-intensive, mission-critical workloads, ensuring superior availability, reliability, security, and performance. 

By facilitating knowledge sharing and rapid learning, the collaboration aims to expedite the success of the indigenous developer community in the HPC space, minimising the need for multiple design iterations and silicon validation, thus reducing timelines.